1. Field of the Invention
The present invention relates to a high-withstand-voltage (high-breakdown voltage) semiconductor device whose main PN junction has a planar structure.
2. Description of the Prior Art
Depending upon the structure of the PN junction, semiconductor devices are classified into the planar type, the mesa type and the bevel type. The planar type has the structure in which all the PN junction ends are exposed in one principal surface of a semiconductor substrate. The mesa type has the structure in which the PN junction end is exposed in an etcheddown surface at the peripheral edge of one principal surface. The bevel type has the structure in which the PN junction end is exposed in a side end surface connecting a pair of principal surfaces, and in which the side end surface intersects the PN junction at an acute angle in some cases and orthogonally in other cases. The planar and mesa types are suitable in the case of forming a number of semiconductor pellets from a semiconductor wafer having a large area, and accordingly they are mainly applied to semiconductor devices requiring only small power. The bevel type is suitable for a high power semiconductor device since it uses a semiconductor substrate large in area as compared with those of the planar and mesa types. From the viewpoint of fabrication, the planar type requires only the diffusion operation, while the mesa type additionally needs the operation of etching down. The bevel type involves an operation for bringing individual devices into the bevel shape. The ease of fabrication is in the order of the planar type, the mesa type and the bevel type.
On the other hand, since the PN junction exposed in the surface of the semiconductor substrate is susceptible to the influence of the atmosphere, it must be stabilized against this influence by covering it with insulating material. The insulating covering is called the passivation film. In the planar and mesa types of semiconductor devices, the passivation film can be formed before splitting the large area semiconductor wafer into many semiconductor pellets, and the efficiency in the formation of the passivation film is excellent. In contrast, in the bevel type of semiconductor device, the passivation film must be formed after such a splitting process. In order to precisely form the passivation film on the small area semiconductor pellets, a high degree of accuracy and much labor are required, so that the bevel type is materially inferior in fabrication efficiency to the planar and mesa types.
A discussion will now be present on the withstand (breakdown) voltages of the respective types. The bevel type can readily achieve a high withstand voltage in such a way that the angle of inclination of the side end surface in which the PN junction is exposed is so set as to make large the sectional area of a region of high impurity concentration which sectional area is taken parallel to the PN junction, namely in such a manner as forming a so-called positive bevel. Moreover, the angle of inclination is 15.degree. - 60.degree. with respect to the PN junction, and the angle does not make the semiconductor substrate become large-sized.
The mesa type has a lower withstand voltage than the bevel type because the surface in which the PN junction is exposed has a negative bevel, that is, the inclined surface is such that the sectional area of a region on the high impurity concentration side relative to the PN junction, which sectional area is taken parallel to the PN junction, becomes small. With the mesa type, a withstand voltage of nearly 900 (V) is attained. In order to attain even higher withstand voltages, the angle of inclination at the position where the PN junction is exposed needs to be made small. The negative bevel has the nature that, as the angle between the inclined surface and the PN junction or the angle of inclination is smaller, the withstand voltage can be made higher. For this reason, in the case of, for example, a thyristor, a PN junction of the positive bevel and a PN junction of the negative bevel are obtained by making the side end surface inclined, the inclination angle of the positive bevel and that of the negative bevel are made different. In the positive bevel the inclination is 15.degree. - 60.degree. as mentioned previously, while in the negative bevel it is 1.degree. - 2.degree.. Accordingly, if a high withstand voltage is intended in the mesa type, the angle of inclination must be made nearly 1.degree. - 2.degree., so that the size of the semiconductor sutstrate becomes very large for a desired conduction current. Also, the withstand voltage is limited far below a desirable level.
In the planar type, the PN junction has a bent portion, at which the field concentrates. Since the impurity concentrations on both sides of the PN junction at its exposed part are high, the spread of a depletion layer becomes small around the exposed part. Due to these facts, it is difficult to obtain a semiconductor device having a high withstand voltage. The withstand voltage attained by the planar type is usually 300 - 400 (V). If a higher withstand voltage is intended with the planar type, a region termed the field limiting ring must be formed on the periphery of the exposed PN junction part, spaced from the PN junction and surrounding it. The withstand voltage as accomplished by the semiconductor device with one field limiting ring is 300 - 400 (V), and the number of the field limiting rings is determined in compliance with a desired rating withstand voltage. Accordingly, as the withstand voltage becomes higher, the number of the field limiting rings increases, which leads to the disadvantage that the semiconductor substrate becomes large-sized for a desired conduction current. The PN junction of the planar type is produced in such a way that the selective diffusion is performed using as a mask an oxide film formed on the semiconductor wafer surface. Since it is difficult to form the oxide film perfectly free from pinholes, diffusion may take place in undesirable portions of the substrate due to the pinholes. Where the diffusion through a pinhole takes place in the surface between the PN junction and the field limiting ring, a depletion layer does not spread to the field limiting ring, and the portion of the diffusion through the pinhole breaks down, so that the desired withstand voltage cannot be acquired. Further, in the planar type semiconductor device, the oxide film used for the mask of the selective diffusion is usually employed as the surface passivation film as it is. Therefore, where the pinholes exist in the oxide film, the semiconductor device is affected by the atmosphere and tends to bring about a degradation in the withstand voltage.
In a planar type semiconductor device which is resin-molded, there is a disadvantage as stated below. With the planar type, it is difficult to thickly form the oxide film as the surface passivation film in view of the generation of cracks and degradation in the precision of mask registration and selective etching. In the device whose withstand voltage is 400 - 500 (V) or higher, an electric field extends even outside the oxide film due to its thinness. Water having permeated through the resin is electrolyzed by the electric field, and the ions thus produced are stuck onto the surface of the oxide film and create an induced channel in the vicinity of the surface of the semiconductor substrate. The induced channel causes leakage current in the device, and makes it impossible to attain a desired withstand voltage.